Evaluation of transition untestable faults using a multi-cycle capture test generation method

Masayoshi Yoshimura, Hiroshi Ogawa, Toshinori Hosokawa, Koji Yamazaki

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

Overtesting induces unnecessary yield loss of VLSIs. Untestable faults, which have no effect on the normal functions of circuits, may be detected in scan testing through scan chains. In this case, the detected untestable faults cause overtesting. Untestable faults consist of uncontrollable faults, unobservable faults, and uncontrollable and unobservable faults. Uncontrollable faults may be detected under invalid states through scan chains by shift-in operations. Unobservable faults cannot be observed at primary outputs, but their effects may be propagated to scan flip-flops. Thus, unobservable faults may be detected through scan chains by shift-out operations. Several methods to reduce the number of detected untestable faults have been proposed. These methods identify invalid states and generate test patterns to avoid invalid states. As a result, the number of detected uncontrollable faults are reduced. However, these methods cannot reduce the number of detected unobservable faults. In this paper, both uncontrollable and unobservable faults are identified using a multi-cycle capture test generation method. We evaluate the relationship between the numbers of untestable faults and the number of time expansions for ISCAS'89 benchmark circuits, and also evaluate factors to identify and classify untestable faults.

本文言語English
ホスト出版物のタイトルProceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010
ページ273-276
ページ数4
DOI
出版ステータスPublished - 2010
イベント13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010 - Vienna, Austria
継続期間: 14 4 201016 4 2010

出版物シリーズ

名前Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010

Conference

Conference13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010
CountryAustria
CityVienna
Period14/04/1016/04/10

フィンガープリント 「Evaluation of transition untestable faults using a multi-cycle capture test generation method」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル