Diagnosing resistive open faults using small delay fault simulation

Koji Yamazaki, Toshiyuki Tsutsumi, Hiroshi Takahashi, Yoshinobu Higami, Hironobu Yotsuyanagi, Masaki Hashizume, Kewal K. Saluja

研究成果: Conference article

1 被引用数 (Scopus)

抄録

Modern high performance, high density integrated circuits use a very large number of metal layers, necessitating the need to deal with the problem of resistive open defects. Resistive opens often manifest as and are modeled as small delay faults. Furthermore, in deep sub-micron technologies, it is known that the additional delay of a line with resistive open fault is not only a function of the resistant of the faulty line but it is also dependent on the signal transition(s) on its adjacent lines. In this paper, we propose an efficient simulation method to simulate small delay faults and we use this simulator to diagnose resistive open faults. The fault simulator developed by us simulates all delay faults for one signal line simultaneously. This information is then used to deduce the candidate faulty lines in two steps. Experimental results for ISCAS'89 benchmark circuits show that by using the method proposed by us the faulty lines can be identified correctly in most cases.

本文言語English
論文番号6690619
ページ(範囲)79-84
ページ数6
ジャーナルProceedings of the Asian Test Symposium
DOI
出版ステータスPublished - 1 1 2013
イベント2013 22nd Asian Test Symposium, ATS 2013 - Yilan, Taiwan, Province of China
継続期間: 18 11 201321 11 2013

フィンガープリント 「Diagnosing resistive open faults using small delay fault simulation」の研究トピックを掘り下げます。これらがまとまってユニークなフィンガープリントを構成します。

引用スタイル