A Design Method for Multiclass Classifiers

Tsutomu Sasao, Yuto Horikawa, Yukihiro Iguchi

研究成果: Conference contribution査読

抄録

Logic minimization is used to design multiclass classifiers for machine learning. This can be an alternative to a neural network. A partially defined classification function f is derived from the training set. Our multiclass classifier correctly classifies not only all the samples in the training set, but also much of samples in the unseen test set. To improve the test accuracy, 1) minimization of variables in f;2) minimization of the number of products in a ternary SOP for f; and 3) maximization of the number of literals in a ternary SOP for f, are performed. Experimental results using MNIST and fashion MNIST data set show that logic minimization improves the test accuracy. Our classifiers can be easily implemented by LUTs and glue logic.

本文言語English
ホスト出版物のタイトルProceedings - 2021 IEEE 51st International Symposium on Multiple-Valued Logic, ISMVL 2021
出版社IEEE Computer Society
ページ148-153
ページ数6
ISBN(電子版)9781728192246
DOI
出版ステータスPublished - 5月 2021
イベント51st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2021 - Virtual, Nur-sultan, Kazakhstan
継続期間: 25 5月 202127 5月 2021

出版物シリーズ

名前Proceedings of The International Symposium on Multiple-Valued Logic
2021-May
ISSN(印刷版)0195-623X

Conference

Conference51st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2021
国/地域Kazakhstan
CityVirtual, Nur-sultan
Period25/05/2127/05/21

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