Simple technique for locating gate-level faults in combinatorial circuits

Teruhiko Yamada, Koji Yamazaki, Edward J. McCluskey

Research output: Contribution to journalConference article

4 Citations (Scopus)


This paper presents a simple technique for locating single gate-level faults in combinatorial circuits. This technique consists of three processes; first, finding possible error sources from the observed errors, second, deducing possible faults from them and finally eliminating faults incapable of being in the circuit under test. Computer simulation was done for ISCAS'85 benchmark circuits to evaluate its performance. The computation time is very short while a high diagnostic resolution may not always be guaranteed. Therefore this would be useful as a preprocess for analyzing the physical defect by various tools such as scanning electron microscopy, electron beam probing and light emission microscopy.

Original languageEnglish
Pages (from-to)65-70
Number of pages6
JournalProceedings of the Asian Test Symposium
Publication statusPublished - 1 Dec 1995
EventProceedings of the 1995 4th Asian Test Symposium - Bangalore, India
Duration: 23 Nov 199524 Nov 1995


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