Reduction in output DC offset voltage of integrator-based filters

Kazuyuki Wada, Shigetaka Takagi, Nobuo Fujii

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Integrator-based filter structures suitable for reduction in DC offset are proposed. First, the effect of DC offset is analyzed by the use of a state space equation. Offset of a filter is the sum of analysis results for all integrators. A simple expression of the filter offset is obtained. The proposed minimization technique of the filter offset derives a lot of filter structures. All the proposed structures for nth-order all-pole low-pass characteristics have the minimum worst-case offset and the minimum variance of offset. Two of the filter structures are chosen to demonstrate the effectiveness of the proposed method.

Original languageEnglish
Title of host publicationProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages17-20
Number of pages4
ISBN (Electronic)0780350081
DOIs
Publication statusPublished - 1 Jan 1998
Event5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998 - Lisboa, Portugal
Duration: 7 Sep 199810 Sep 1998

Publication series

NameProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
Volume2

Conference

Conference5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998
CountryPortugal
CityLisboa
Period7/09/9810/09/98

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Wada, K., Takagi, S., & Fujii, N. (1998). Reduction in output DC offset voltage of integrator-based filters. In Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems (pp. 17-20). [814812] (Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems; Vol. 2). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICECS.1998.814812