With the scaling of VLSI feature size and increasing complexity of VLSI, it is difficult to determine the cause of failurein a chip. Most of the studies on failure analysis have assumed one fault model, such as single/multiple stuck-at, bridging, or open faults. However, we do not know which fault model can explain a behavior of the defect in the circuit under test before starting diagnosis. Moreover, under Built-In Self Test (BIST) environment, it is difficult to know which primary output has a faulty response on the application of a failing test. In this paper, we propose an effective diagnostic method in the presence of unknown fault model, based on only pass/fail information on the applied tests. The proposed method deduces faulty conditions that are able to explain the behavior of the defect in the circuit and locates faulty sites, based on the number of detections for the single stuck-at fault at each line, by performing single stuck-at fault simulation with both passing and failing tests. As a result, we can derive a fault model from the faulty condition. To improve the ability of fault diagnosis, our method uses the logic values of lines and the condition whether the stuck-at faults at the lines are detected or not by passing and failing tests. Experimental results show that our method can accurately identify the fault models for 93% faulty circuits and that the faulty sites are located within several candidates except for circuits with multiple stuckat faults.
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 1 Dec 2005|
|Event||IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan|
Duration: 23 May 2005 → 26 May 2005