This paper proposes a novel area-efficient and cost-effective design methodology for MOSFET-C continuous-time filters. The new methodology reduces the number of MOS transistors used in the previously reported work by almost a factor of two. A third-order leapfrog low-pass Chebyschev filter is realized and simulated as an example to demonstrate the validity of the new design methodology.
|Number of pages||4|
|Publication status||Published - 1 Dec 1996|
|Event||Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems - Seoul, South Korea|
Duration: 18 Nov 1996 → 21 Nov 1996
|Conference||Proceedings of the 1996 IEEE Asia Pacific Conference on Circuits and Systems|
|City||Seoul, South Korea|
|Period||18/11/96 → 21/11/96|