Four-terminal double-gate logic for LSTP applications below 32-nm technology node

S. O'uchi, Y. X. Liu, M. Masahara, Toshiyuki Tsutsumi, K. Endo, T. Nakagawa, M. Hioki, T. Sekigawa, H. Koike, E. Suzuki

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A logic system consisting of four-terminal double-gate MSOFETs (4T-DGFETs) suppresses power consumption while it also improves processing efficiency by utilizing a flexible threshold-voltage control function by a second gate of 4T-DGFET. Based on the simulation calibrated with the fabricated device characteristics, it is shown that the 4T-DGFET logic is effective in low-standby-power applications below the half-pitch (hp) 32-nm technology node, A scaling strategy for the 4T-DG logic is also provided.

Original languageEnglish
Title of host publication2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06
Publication statusPublished - 1 Dec 2006
EventIntegrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference - Padova, Italy
Duration: 24 May 200626 May 2006

Publication series

Name2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06

Conference

ConferenceIntegrated Circuit Design and Technology, 2006. ICICDT '06. 2006 IEEE International Conference
CountryItaly
CityPadova
Period24/05/0626/05/06

    Fingerprint

Keywords

  • 4T-DGFET
  • Fin
  • TCAD mixed mode and LSTP
  • Threshold voltage control technique

Cite this

O'uchi, S., Liu, Y. X., Masahara, M., Tsutsumi, T., Endo, K., Nakagawa, T., ... Suzuki, E. (2006). Four-terminal double-gate logic for LSTP applications below 32-nm technology node. In 2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06 [1669388] (2006 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT'06).