Fin-height effect on poly-Si/PVD-TiN stacked-gate FinFET performance

Tetsuro Hayashida, Kazuhiko Endo, Yongxun Liu, Shin Ichi O'Uchi, Takashi Matsukawa, Wataru Mizubayashi, Shinji Migita, Yukinori Morita, Hiroyuki Ota, Hiroki Hashiguchi, Daisuke Kosemura, Takahiro Kamei, Junichi Tsukada, Yuki Ishikawa, Hiromi Yamauchi, Atusi Ogura, Meishoku Masahara

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

We compared the electrical characteristics, including mobility and on -state current I on, of n +-poly-Si/PVD-TiN stacked-gate FinFETs with different fin heights H fin. The mobility was enhanced in devices with taller fins due to increased tensile stress. However, as gate length L g decreases, I on for devices with tall fins becomes worse, probably due to a high parasitic resistance R p. Furthermore, V th variation increased with increasing H fin due to rough etching of the fin sidewall. Process technologies for reducing R p and etching technology that yields smooth precise profiles are essential to exploit the high performance of tall FinFETs.

Original languageEnglish
Article number6148269
Pages (from-to)647-653
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume59
Issue number3
DOIs
Publication statusPublished - 1 Mar 2012

Keywords

  • fin height
  • FinFET
  • mobility
  • parasitic resistance titanium nitride (TiN)

Cite this

Hayashida, T., Endo, K., Liu, Y., O'Uchi, S. I., Matsukawa, T., Mizubayashi, W., ... Masahara, M. (2012). Fin-height effect on poly-Si/PVD-TiN stacked-gate FinFET performance. IEEE Transactions on Electron Devices, 59(3), 647-653. [6148269]. https://doi.org/10.1109/TED.2011.2181385