Mario Tokoro, Hideki Mori, Noriyuki Kaneko, Motoo Shimada, Shun ichi Uchida, Hideo Aiso

Research output: Contribution to journalArticlepeer-review


A description is given of the fast Fourier transform (FFT) in a high-speed Keio signal processor (KSP) and the hardware realization of the FFT. The KSP is a signal processing computer whose fundamental function is the FFT. In order to realize high-speed processing ability and operational and structural flexibility, KSP adopts a pipeline processing system, bus construction and microprogrammed control system. The Sande algorithm is used ″in place″ to perform FFT. The pipeline processing employs the FFT arithmetic unit and a 3-bank memory device. The FFT arithmetic unit consists of an arithmetic unit for complex numbers (CAU) and data recording units and is realized by four stages of pipelines. The CAU performs fixed-point arithmetic operations. Overlfows are prevented and a proposal to minimize truncation is realized. A bit-reversal circuit is used to generate memory addresses for the FFT arithmetic. An idea is implemented which simplifies address generation for various arithmetic units of different pipeline lengths.

Original languageEnglish
Pages (from-to)58-67
Number of pages10
JournalSyst Comput Controls
Issue number5
Publication statusPublished - 1 Jan 1975


Dive into the research topics of 'FAST FOURIER TRANSFORM BY HARDWARE.'. Together they form a unique fingerprint.

Cite this