A Design Method for Multiclass Classifiers

Tsutomu Sasao, Yuto Horikawa, Yukihiro Iguchi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

Logic minimization is used to design multiclass classifiers for machine learning. This can be an alternative to a neural network. A partially defined classification function f is derived from the training set. Our multiclass classifier correctly classifies not only all the samples in the training set, but also much of samples in the unseen test set. To improve the test accuracy, 1) minimization of variables in f;2) minimization of the number of products in a ternary SOP for f; and 3) maximization of the number of literals in a ternary SOP for f, are performed. Experimental results using MNIST and fashion MNIST data set show that logic minimization improves the test accuracy. Our classifiers can be easily implemented by LUTs and glue logic.

Original languageEnglish
Title of host publicationProceedings - 2021 IEEE 51st International Symposium on Multiple-Valued Logic, ISMVL 2021
PublisherIEEE Computer Society
Pages148-153
Number of pages6
ISBN (Electronic)9781728192246
DOIs
Publication statusPublished - May 2021
Event51st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2021 - Virtual, Nur-sultan, Kazakhstan
Duration: 25 May 202127 May 2021

Publication series

NameProceedings of The International Symposium on Multiple-Valued Logic
Volume2021-May
ISSN (Print)0195-623X

Conference

Conference51st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2021
Country/TerritoryKazakhstan
CityVirtual, Nur-sultan
Period25/05/2127/05/21

Keywords

  • classification
  • digit recognition
  • generalization ability
  • machine learning
  • MNIST
  • neural network
  • partially defined function
  • support minimization
  • ternary logic

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