• 69 Citations
  • 5 h-Index
1991 …2017

Research output per year

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Research Output

  • 69 Citations
  • 5 h-Index
  • 11 Conference contribution
  • 7 Article
  • 6 Conference article

A diagnostic fault simulation method for a single universal logical fault model

Hosokawa, T., Takano, H., Yamazaki, H. & Yamazaki, K., 5 May 2017, Proceedings - 2017 IEEE 22nd Pacific Rim International Symposium on Dependable Computing, PRDC 2017. Kitakami, M., Kim, D. S. & Varadharajan, V. (eds.). IEEE Computer Society, p. 217-218 2 p. 7920618. (Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 3 Citations (Scopus)

    Diagnosing resistive open faults using small delay fault simulation

    Yamazaki, K., Tsutsumi, T., Takahashi, H., Higami, Y., Yotsuyanagi, H., Hashizume, M. & Saluja, K. K., 1 Jan 2013, In : Proceedings of the Asian Test Symposium. p. 79-84 6 p., 6690619.

    Research output: Contribution to journalConference article

  • 1 Citation (Scopus)

    A method for diagnosing resistive open faults with considering adjacent lines

    Takahashi, H., Higami, Y., Takamatsu, Y., Yamazaki, K., Tsutsumi, T., Yotsuyanagi, H. & Hashizume, M., 1 Dec 2010, ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies. p. 609-614 6 p. 5665061. (ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 6 Citations (Scopus)

    Evaluation of transition untestable faults using a multi-cycle capture test generation method

    Yoshimura, M., Ogawa, H., Hosokawa, T. & Yamazaki, K., 30 Jul 2010, Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010. p. 273-276 4 p. 5491771. (Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

  • 1 Citation (Scopus)

    Output voltage estimation of a floating interconnect line caused by a hard open in 90nm ICs

    Manabe, K., Yamada, Y., Yotsuyanagi, H., Tsutsumi, T., Yamazaki, K., Higami, Y., Takahashi, H., Takamatsu, Y. & Hashizume, M., 1 Dec 2010, ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies. p. 603-608 6 p. 5665062. (ISCIT 2010 - 2010 10th International Symposium on Communications and Information Technologies).

    Research output: Chapter in Book/Report/Conference proceedingConference contribution